1. Field of the Invention
The present invention relates to data processing systems, and more particularly to clock systems which control timing in data processing systems.
2. Prior Art
There are many clock system designs available to control the timing of a data processing system. The following patents are representative of the prior art and indicate some of the problems to be overcome.
U.S. Pat. No. 5,371,772 entitled "Programmable Divider Exhibiting a 50/50 Duty Cycle," teaches the division of a system reference clock signal by a programmer integer value. A storage register stores the value equal to the desired divisor minus 2. Thus, a stored value of 0 results in a divided by 2. It is not clear that divide by 1 can be achieved as an option in the system shown in the patent.
Control logic controls the output duty cycle to be 50/50 by toggling a flip-flop to coincide with system clock edges. This requires that the symmetry of the output signal is dependent upon the symmetry of the clock reference input signal.
The present invention provides for an option of a divide by 1 as well as having an output signal symmetry being independent of the input signal symmetry and also includes a frequency doubler on the input signal which is not taught in the referenced patent.
U.S. Pat. No. 4,318,045, entitled "Symmetrical Waveform Signal Generator Having Coherent Frequency Shift Capability," teaches an apparatus for generating a signal having a symmetrical waveform of frequency selectable according to a plurality of input signals. The frequency of the signal changes rapidly in response to changes in the input signals and changes occur in a coherent manner with no perturbation of the output signal. A high speed clock signal and the signals generated by its successive divisions are logically combined to produce a plurality of signals which are filtered to produce substantially symmetrical waveform signals which are maintained in periodic phase coherence.
As discussed above, the '045 patent depends on input signal symmetry to provide symmetry of the output clock signal. Further, the clock circuit taught by the '045 patent does not provide the 50/50 output symmetry of the present invention, nor does the '045 patent teach the use of a frequency doubler circuit on the input clock signal to facilitate division by odd integers.
U.S. Pat. No. 4,935,944 entitled "Frequency Divider Circuit with Integer and Noninteger Divisors," teaches a frequency divider circuit including a polynomial counter, decode logic, and a clock edge selector. The polynomial counter, in response to a clock signal at a predetermined frequency, cycles through a predetermined set of logic states which are logical combinations of the previous state and generates a set of output signals which indicates the present logic state of the polynomial counter. The decode logic, responsive to output signals of the polynomial counter implements a predetermined logical mapping of the output signals into a decoded output signal. The clock edge selector responsive to the decoded output signal of the decode logic utilizes flip-flops and other logic to generate integer and noninteger multiples of the clock signal. The frequency divider circuit selects either integer or noninteger divisors, depending on the information content of a control signal.
As discussed above, the '944 patent depends upon symmetry of the input clock signal to control symmetry of the output signal. Further the '944 patent does not teach a dynamically or synchronously switching division ration, but rather is limited to a fixed predetermined integer or noninteger divisor. Additionally, the '944 patent does not teach a frequency multiplier on the input clock signal.
U.S. Pat. No. 3,701,027 entitled "Digital Frequency Synthesizer", teaches a circuit for simultaneously generating a plurality of signals at related frequencies. A clock source having a frequency greater than the frequency of any of the signals to be generated is applied to an in put of a scalar circuit. The scalar circuit generates a plurality of output signals, there being an output signal from the scalar circuit corresponding to each of the related frequency signals to be generated. Some of the signals from the scalar have non uniform pulse-to-pulse spacing. The outputs of the scalar circuit are converted to signals at the desired frequencies with substantially uniform pulse-to-pulse spacing.
The '027 patent does not teach a clocking system having a 50/50 output symmetry independent of input clock symmetry. Further, the '027 patent does not teach the capability of dynamically and synchronously switching division ration.
In addition, there is no frequency multiplier shown on the input clock signal.
U.S. Pat. No. 5,065,415 entitled "Programmable Frequency Divider", teaches a frequency divider for dividing the frequency of a supplied high frequency signal directly into lower frequency signals and includes a number of prescalars or programmable frequency divider units each capable of being switched between divide by 2 and divide by 3 modes. The prescalars are connected in cascade for producing an output signal which is frequency divided at one or a multiple of division ratios at a time.
Although the '415 patent teaches a programmable frequency divider, it does not mention output symmetry and does not each an output symmetry which is not dependent upon input symmetry to provide a 50/50 output signal. Further, the frequency divider of the '415 patent does not teach nor suggest the possibility of a divide by 1 which can be very useful at power on time in a data processing system. Additionally, the '415 patent does not teach the use of a frequency multiplier on the input clock signal, nor is there any mention of controlling output delay regardless of division ratio which can be very important which dividers are used in clock distribution systems or as part of feedback loops.
U.S. Pat. No. 4,891,825 entitled "Fully Synchronized Programmable Counter With a Near 50% Duty Cycle Output Signal", shows a method and apparatus to generate a fully synchronized programmable frequency divider output having a near 50% duty cycle output signal independent of the divisor, whether odd or even, and suitable for use in phase lock loop frequency synthesizers.
Although the '825 patent has a near 50% duty cycle output signal independent of the divisor, the symmetry is not independent of the input clock symmetry as in the invention to be described and claimed herein. Further, the system shown in the '825 patent does not include a frequency multiplier on the input clocking signal.
U.S. Pat. No. 5,313,509 entitled "Pulse Counter With Arbitrary Output Characteristics", teaches a pulse counter having a programmable prescalar which divides the frequency of an input clock signal by a factor designated by a signal from a code generator which encodes count output from a programmable prescalar to generate the code signal which controls the programmable prescalar.
The counter of the '509 patent does not appropriate address the output symmetry issues in clocking systems, nor does the '509 patent address the problems of maintaining consent output delay regardless of division ratio which, as identified above, is very important when division is used in clock distribution systems. Further, the '509 patent does not include a frequency multiplier on the input clock line.
U.S. Pat. No. 5,253,279 entitled "Semiconductor Integrated Circuit Having a Built-In programmable Divider", teaches an input terminal provided for each of the output terminals such that the input circuit outputs either a high or low as a frequency dividing ratio setting signal when the corresponding input terminal is high or low, but outputs another one of high or low as a frequency dividing ratio setting signal when the corresponding input terminal is in an open state.
Although the '279 patent teaches a programmable frequency divider, it does not teach important aspects of the invention taught and claimed herein with respect to output symmetry independent of input signal symmetry, the capability of dynamically and synchronously switching frequency division ratio, nor the maintenance of constant output delay regardless of division ratio.